Lattice Semiconductor
PCI Express User’s Guide
Transmit DLLP Block
The Transmit DLLP processing block, generates ACK or NAK DLLPS based on the instructions from the Receive
TLP processing block. This block also generates InitFC DLLPs corresponding to FCI requirements. Appropriate
power management DLLPs are generated as instructed by external power management logic. This block consists
of a 16-bit CRC generation logic that adds the calculated CRC to the tail of all transmit DLLPs to meet data integrity
requirements.
Receive Path
Receive TLP Block
Receive TLP processing block implements sequence number checking, data integrity checking, and through LCRC
checking for received TLPs. It includes an appropriate retry mechanism to respond to any errors detected in
received TLPs. This block is provided with a buffering mechanism to hold the whole TLP until its data integrity is
checked and an appropriate instruction is generated to the Transmit DLLP block to send ACK and NAK DLLPs.
Associated retry logic implements the time-out mechanism as speci?ed in the PCI Express speci?cation. After all
these Data Link Layer requirements for a TLP are met the TLPs are sent out over Receive TLP interface to the
transaction layer.
Receive DLLP Block
The main function implemented in this block is related to the processing of all incoming DLLPs as listed below:
? Data integrity checking of all DLLPs through CRC checking.
? Detection of different types of DLLPs through DLLP type decode.
? Extraction of different ?elds of DLLPs based on the type of the DLLP decoded.
? ACK and NAK processing.
In case of CRC error the DLLP is discarded and the error is transmitted to the user logic.
If the DLLP passes data integrity checking it is processed as described below:
? ACK DLLP: TLP Sequence number received in this DLLP indicates successful receipt of TLPs up to this
Sequence number. This information is passed to the transmit TLP processing block to manage its transmit retry
mechanism.
? NAK DLLP: This TLP sequence number negative acknowledgement initiates a Data Link Layer retry by the
transmit TLP processing block using its transmit retry mechanism.
? InitFC1, InitFC2 and UpdateFC DLLPs: Used for Flow Control Initialization and Credit Calculation.
? Power Management DLLP: PM request type is extracted from this DLLP and is made available in the User
Interface side.
Receive User Interface
All Receive transactions to the user interface are synchronized with the rising edge of the div2_pclk . Signal
transactions between the core and the user interface are carried out in the form of received TLPs. Apart from the
received data the core also provides status of the received TLPs and DLLPs. In case of error during reception of a
TLP or DLLP a corresponding error signal is asserted to notify the user interface.
Rx TLPs are output by the core through a 32-bit data bus, rxtlpu_data . The following handshake signals are
provided to ensure a smooth and controlled interface between the core and the user interface.
rxtlpu_st – The core loads the ?rst DWORD of the TLP and asserts this output signal to indicate the start
of Rx TLP. All remaining parts of the TLP are loaded out of the core in subsequent clocks. The core at the
positive edge of the div2_pclk clock, sends out each DWORD of the TLP.
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相关PDF资料
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